At the European Economic Congress 2026 (EEC 2026) in Katowice, Poland, MICROIP chairman Dr. James Yang outlined a "software-driven hardware" strategy for AI deployment, paired with a partnership to build a resilient supply chain for edge ASICs in Europe. The announcement, made during the Poland-Taiwan Economic Cooperation Forum, positions Poland as a strategic hub for edge AI hardware, leveraging Taiwan’s semiconductor expertise and Poland’s software talent.
Overview
MICROIP, a Taiwanese ASIC design services and AI software company, advocates for translating domain knowledge directly into silicon rather than relying on general-purpose chips. The company’s approach uses conventional chip platforms combined with its low-power custom ASIC design service (CATS) and the no-code AIVO platform. This allows engineers to turn industry-specific knowledge into specialized applications with minimal barriers, according to Yang.
The company claims commercial success in autonomous UAV navigation (object tracking without internet access) and smart city deployments, where on-device processing preserves privacy and saves bandwidth.
The partnership
At the forum, Yang was joined by Ambassador Liu Yong-jian and HCG vice president Michael Chiu. Chiu identified Poland as a key innovation partner for Taiwan’s security industry. The collaboration aims to combine what Yang called Poland’s "soft intelligence" with Taiwan’s "hard fundamentals" — specifically, European software talent with Taiwanese hardware capabilities to create a "resilient supply chain."
MICROIP also collaborates with its sister company Arculus EDA UK to provide professional EDA services. This alliance, Yang said, reduces the R&D-to-mass-production cycle for ASICs, enabling MICROIP to co-define global AIoT standards while offering European customers cost-effective solutions for local market needs.
The software-driven hardware model
The core of MICROIP’s strategy is the "software-driven hardware" concept. Yang argued that global AI adoption is hindered by fragmented end-user demands and the high cost of general-purpose chips. By using CATS and AIVO, engineers can create custom ASICs tailored to specific edge AI tasks — such as real-time object tracking or privacy-preserving smart city sensors — without needing deep hardware expertise.
This model has already demonstrated commercial viability in UAV navigation (offline object tracking) and smart city applications, where on-device processing reduces bandwidth usage and protects data privacy.
Tradeoffs
While the software-driven hardware approach reduces development barriers, it still requires domain expertise to define the application logic. The no-code platform lowers the entry point, but the final ASIC design cycle — even with EDA support from Arculus — remains longer than using off-the-shelf chips. Additionally, the partnership’s success depends on Poland’s ability to scale semiconductor manufacturing infrastructure in the Katowice region, which is still developing compared to established Asian fabs.
Bottom line
MICROIP’s strategy is a practical bet on edge AI’s fragmentation: instead of one-size-fits-all chips, the company offers a path to custom silicon for specific use cases. The Poland partnership provides access to European talent and a potential manufacturing base, but the real test will be whether the reduced development cycle and cost savings outweigh the inherent complexity of ASIC design for smaller-scale deployments.