At the 2026 European Economic Congress (EEC 2026) in Katowice, Poland, MICROIP Chairman Dr. James Yang outlined a strategy to decouple edge-AI hardware from Taiwan’s foundry dominance by co-developing RISC-V-based ASICs with Polish fabs and open-source toolchains. The approach, described as “Software-Driven Hardware,” aims to deliver sub-10ms latency inference for industrial IoT while sidestepping U.S. export controls on advanced lithography.
Overview
MICROIP, a Taiwan-based ASIC design services and AI software company, is partnering with Polish semiconductor fabs and leveraging EU Chips Act subsidies to build a resilient supply chain for edge AI. The strategy pivots on translating domain-specific software expertise into custom silicon, using MICROIP’s low-power Customized ASIC Design Services (CATS) and AIVO No-Code platform. A 2027 pilot of 5nm-capable nodes in Gdańsk is planned, aiming to undercut TSMC’s lead in advanced nodes.
What it does
The “Software-Driven Hardware” model allows engineers to transform industry-specific knowledge into specialized applications with minimal barriers. MICROIP uses mainstream chip platforms alongside its CATS and AIVO platforms to create custom ASICs. This has already demonstrated commercial success in autonomous UAV navigation—tracking objects without internet access—and in smart cities, where on-device processing protects privacy and saves bandwidth.
The partnership
At the EEC forum, Dr. Yang was joined by Ambassador Liu Yong-jian and HCG Vice Chairman Michael Chiu. Chiu identified Poland as a core innovation partner for Taiwan’s security industry. Yang noted that combining Europe’s software talent with Taiwan’s hardware creates a “resilient supply chain,” establishing Poland as an “AI Hardware-Software Innovation Hub.” MICROIP also collaborates with its sister company, Arculus System, to provide professional EDA services, reducing the ASIC R&D-to-mass-production cycle.
Tradeoffs
The strategy sidesteps U.S. export controls on advanced lithography by using open-source RISC-V architectures and Polish fabs. However, it depends on EU Chips Act subsidies and the successful ramp of 5nm-capable nodes in Gdańsk by 2027. The approach also requires deep integration of European software talent with Taiwanese hardware expertise—a cultural and logistical challenge.
When to use it
This model is relevant for companies deploying edge AI in industrial IoT, autonomous systems, and smart city infrastructure where latency, privacy, and supply-chain resilience matter. It is less suited for high-volume consumer chips where TSMC’s scale and cost advantages remain dominant.
Bottom line
MICROIP’s strategy offers a practical path for European companies to build sovereign edge-AI hardware without relying on Taiwan’s foundries or U.S. export-controlled lithography. Success depends on the 2027 pilot and the depth of Poland-Taiwan talent integration.